1. Field of the Invention
The present invention generally relates to the field of transistors, and more particularly, to a transistor having strained silicon.
2. Description of the Prior Art
As semiconductor devices' switching speeds continue to increase and operating voltage levels continue to decrease, the performances of metal-oxide-semiconductor field effect transistors (MOSFETs) and other types of transistors, such as bipolar junction transistors, need to be correspondingly improved. Currently, along with the development of the MOSFETs, one of the main goals is to increase the carriers' mobility so as to further increase the operation speed of the MOSFETs.
In general, a MOSFET is disposed on a semiconductor substrate, which has at least a gate structure, a source region, a drain region separately disposed on two sides of the gate structure and a channel region disposed in the semiconductor substrate right below the gate structure. When a voltage with a certain value is applied to the gate structure, the resistance of the channel region decreases correspondingly, due to the induced capacitance effect and to the carriers that are able to flow between the source region and the drain region freely. In theory, it is well-known that the mobility of carriers flowing in the channel region can be affected by a lattice structure within the channel region. In order to get benefits from this phenomenon, in the current fabrication processes, a stress layer with a certain stress will be formed on a semiconductor substrate to cover a corresponding gate structure, a source region and a drain region. Since the stress layer is able to cover the regions (the gate structure, the source region and the drain region) conformally, the inherent stress within the stress region can be therefore transferred or applied to a channel region right below the gate structure. As a result, the operation speed of a corresponding MOSFET is increased thanks to the enhanced carrier mobility. By way of example, the stress layer within an N-type MOSFET may be a layer with a tensile stress. This tensile stress can enlarge the interstitial space within the lattice structure and raise the carrier mobility of the N-type MOSFET.
With these continuously increasing operation speeds of the MOSFET, the current procedure for fabricating the stress layer reaches its limits. In parts of the N-type MOSFET, in order to further raise the tensile stress applied to the channel region, an inherent tensile stress within the stress layer can be increased by modulating factors for depositing the stress layer. The tensile stress of the stress layer, however, has a maximum value, such as 1.52 Giga pascals (Gpa). Once the tensile stress exceeds this maximum value, the tensile stress layer is likely to fracture and the yield of the corresponding MOSFET is therefore reduced.
Therefore, there is a need to provide a MOSFET and a fabricating method thereof so that the stress of a stress layer can be transferred to a corresponding channel region more effectively without the occurrence of fractures in the stress layer.